EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0A fpga_0_BTNs_4Bit_GPIO_in_pin I 0:2 fpga_0_BTNs_4Bit_GPIO_in 1B fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin I 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I 2B fpga_0_DDR2_SDRAM_DDR2_DQ IO 15:0 fpga_0_DDR2_SDRAM_DDR2_DQ 3B fpga_0_DDR2_SDRAM_DDR2_DQS IO 1:0 fpga_0_DDR2_SDRAM_DDR2_DQS 4B fpga_0_DDR2_SDRAM_DDR2_DQS_n IO 1:0 fpga_0_DDR2_SDRAM_DDR2_DQS_n 5B fpga_0_DDR2_SDRAM_DDR2_Addr_pin O 12:0 fpga_0_DDR2_SDRAM_DDR2_Addr 6B fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_BankAddr 7B fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_n 8B fpga_0_DDR2_SDRAM_DDR2_CE_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CE 9B fpga_0_DDR2_SDRAM_DDR2_CS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CS_n 10B fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk_n 11B fpga_0_DDR2_SDRAM_DDR2_Clk_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk 12B fpga_0_DDR2_SDRAM_DDR2_DM_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_DM 13B fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin O 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O 14B fpga_0_DDR2_SDRAM_DDR2_ODT_pin O 1 fpga_0_DDR2_SDRAM_DDR2_ODT 15B fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_n 16B fpga_0_DDR2_SDRAM_DDR2_WE_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_WE_n 17C fpga_0_DIPs_4Bit_GPIO_in_pin I 0:3 fpga_0_DIPs_4Bit_GPIO_in 18D fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col 19D fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 20D fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv 21D fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk 22D fpga_0_Ethernet_MAC_PHY_rx_data_pin I 3:0 fpga_0_Ethernet_MAC_PHY_rx_data 23D fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er 24D fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk 25D fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n 26D fpga_0_Ethernet_MAC_PHY_tx_data_pin O 3:0 fpga_0_Ethernet_MAC_PHY_tx_data 27D fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en 28E fpga_0_LEDs_8Bit_GPIO_d_out_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_d_out 29F fpga_0_RS232_DCE_RX_pin I 1 fpga_0_RS232_DCE_RX 30F fpga_0_RS232_DCE_TX_pin O 1 fpga_0_RS232_DCE_TX 31G fpga_0_RS232_DTE_RX_pin I 1 fpga_0_RS232_DTE_RX 32G fpga_0_RS232_DTE_TX_pin O 1 fpga_0_RS232_DTE_TX 33H fpga_0_SPI_FLASH_MISO_pin IO 1 fpga_0_SPI_FLASH_MISO 34H fpga_0_SPI_FLASH_MOSI_pin IO 1 fpga_0_SPI_FLASH_MOSI 35H fpga_0_SPI_FLASH_SCK_pin IO 1 fpga_0_SPI_FLASH_SCK 36H fpga_0_SPI_FLASH_SS_pin IO 0:1 fpga_0_SPI_FLASH_SS 37I sys_clk_pin I 1 dcm_clk_s  CLK  38J sys_rst_pin I 1 sys_rst_s  RESET